KA670 CPU Module Technical Manual

This document is the KA670 CPU Module Technical Manual, published by Digital Equipment Corporation in April 1990. It serves as a comprehensive technical reference for the KA670 CPU module and the associated MS670 memory expansion modules, intended for design engineers and applications programmers familiar with the Q22-bus and VAX instruction set.

The manual covers:

1. Overview and Installation: Introduces the KA670 CPU (a quad-height VAX processor for Q22-bus, supporting high-speed, real-time, and multiuser environments), its two versions (KA670-AA and KA670-BA, with the latter not supporting multiuser OS licenses), major hardware components (P-chip CPU, F-chip FPA, C-chip cache controller, G-chip memory controller, Q22-bus, Ethernet, and DSSI interfaces), MS670 memory modules, and the H3604 console module. It also details installation procedures and configuration aspects like node naming and DSSI unit numbers.

2. Architecture:

   • Central Processor and Floating Point Unit: Describes the P-chip (DC520) responsible for VAX instruction set execution, memory management, general-purpose and internal processor registers. It also details the F-chip (DC523) floating-point accelerator, its data types, instructions, and operand transfer.
   • Cache and Main Memory: Explains the KA670's two-level cache hierarchy (primary on-chip, backup external) including organization, address translation, data allocation, write behavior, and error recovery. It also covers the G-chip (DC561) main memory controller, its ports, write buffers, and error detection (e.g., modified Hamming code).
   • Console Line, TOY Clock, and Bus System: Details the console serial line, time-of-year (TODR) and interval timers (ICCS), and provides an overview of the RDAL, CP, and GMI bus systems and their components.

3. Boot and Diagnostic Facility: Describes the boot and diagnostic registers (BDR, DLEDR), EPROM firmware, battery-backed RAM, and various initialization sequences (power-up, hardware reset, I/O bus, processor). It outlines power-up modes, diagnostic functions, and error reporting.

4. Interface Subsystems: Provides in-depth information on the KA670's interfaces:

   • Q22-bus Interface (CQBIC): Covers address translation, map registers, interprocessor communication, interrupt handling, and error reporting.
   • Ethernet Interface (SGEC): Discusses the network interface, station address ROM, programming the SGEC chip, startup procedures, and handling of reception and transmission processes.
   • Mass Storage Interface (SHAC): Explains the DSSI bus interfaces, CI-DSSI overview, and SHAC registers.

5. Error Handling: A significant portion is dedicated to unexpected system error exceptions and interrupts. It categorizes errors (machine check, power-fail, hard/soft interrupts, kernel stack not valid), explains information saved on machine check exceptions, and outlines macrocode error handling and recovery procedures.

The document also includes extensive appendices detailing:

• Q22-bus specifications (signals, data transfer, DMA, interrupts, electrical characteristics).
• Physical, electrical, and environmental specifications of the modules.
• Memory and I/O address assignments.
• A reference to the VAX instruction set.
• The machine state on power-up.
• Maintenance Operation Protocol (MOP) support.
• ROM and RAM partitioning.
• Internal data structures used by the firmware.
• A comprehensive list of error messages.

In essence, it's a deep dive into the hardware, firmware, and low-level software aspects necessary to design for, install, configure, and troubleshoot the KA670 CPU module within Digital Equipment Corporation's VAX systems.