DEC STD 160

This document, DEC Standard 160, is a comprehensive technical specification for the LSI-11 Bus, divided into two main sections: a design specification for current systems and a historical reference for older versions.

Section 0: Design Specification (current as of 17-Sep-81) This section provides the essential information for interfacing with the LSI-11 Bus, specifically covering the 1980 version, which includes 22 bits of address space and block mode transfers. Key aspects include:

• Purpose and Scope: Defines the LSI-11 Bus as an interconnection medium for system components, ensuring compatibility for new designs.
• Bus Signals: Details the 42 signal lines, their functions (e.g., Data/Address, Memory Parity, Control, DMA, Interrupt, System Control), and pin assignments. All signals are asserted low and negated high, except for BPOK and BDCOK.
• Electrical Characteristics: Specifies design goals for the Q-Bus (expandability, controlled characteristics, minimal signals), and provides theoretical design parameters for backplanes (impedance, resistance, maximum number), interconnect cables (impedance, length, crosstalk), connection points, and bus drivers/receivers (voltage ranges, propagation delay, skew, noise immunity, loading, termination). It also outlines power failure control signals.

• Bus Protocols: Describes the sequences of events for various bus transactions:

  • Power Up/Down: Initialization of devices and processor control during power changes.
  • Initialization: Resetting bus devices to a known state.
  • Boot: Hardware and software boot procedures.
  • Data and Address Structure: Defines 16-bit word data and address spaces (16-, 18-, and 22-bit physical addressing for I/O and memory), including special 30KW systems.
  • Bus Mastership (DMA): Acquisition and relinquishment of bus control, and various data transfer cycles (DATI, DATO, DATOB, DATIO, DATIOB, DATBI, DATBO, Refresh).
  • Interrupt Protocol: How devices request and receive interrupt service from the processor, including priority schemes.
  • Event and HALT Protocols: Special interrupt conditions and processor halt state.

• Environmental Requirements: Standards for bus operation.

• Functional Descriptions: Detailed explanation of each bus signal.
• Appendix A (Q22-Bus Parity): Describes an optional single-bit parity protocol for address and data transfers on the Q22-Bus.

Section 1: History of the LSI-11 Bus This section serves as a historical reference for earlier versions of the LSI-11 Bus (16-bit and 18-bit address versions) and is explicitly stated as not a design specification for new products, but rather useful for ensuring backward compatibility. It highlights:

• Evolution: Describes the bus's development from 16- and 18-bit versions.
• Major Differences: Points out variations in bus signal lines (older versions used 38 vs. 42), power down and DATO protocol exceptions for older CPUs.
• Electrical Deviations: Lists older backplane types with different characteristic impedances and notes deviations in cable specifications and driver/receiver specifications for earlier hardware.
• System Configuration and Power: Discusses considerations for configuring bus options for performance, and details power distribution, regulation, and battery backup.
• Address Assignments: Provides historical interrupt and trap vectors, and device address assignments for both Unibus and LSI-11 Bus.