DEC STD 157

This document, DEC Standard 157, is the OMNIBUS Specification, providing a detailed description of the mechanical, electrical, and logical characteristics of the OMNIBUS bus scheme. Its primary purpose is to serve as a guide for anyone designing devices intended to connect to the OMNIBUS in the DEC PDP-8E, PDP-8M, PDP-8F, and PDP-8A series of mini-computers.

Key aspects covered in the specification include:

1. General Description: Defines the OMNIBUS as an internal, parallel bus used for interconnecting central processors, memories, and peripherals. It specifies the physical connectors (DEC H863) and general pin assignments.
2. Major Signal Groups: Divides the 96 OMNIBUS signals into nine main categories:
   • Memory Address (MA, EMA): For defining the active memory address, sourced by the CPU or DMA devices.
   • Memory Data and Direction Control (MD, MD DIR L): A bidirectional data path between memory and CPU, with a control line to specify data direction.
   • Data Bus (DATA): A multi-purpose 12-bit bus for data exchange, DMA input, front-panel monitoring, and data break priority.
   • I/O Control Signals: Govern the CPU-peripheral I/O dialogue and include signals like INITIALIZE H for clearing flags.
   • DMA Control Signals: Manage data break (Direct Memory Access) operations, which allow peripherals to communicate directly with memory.
   • Timing Signals: System clocks and enabling levels (e.g., time pulses TPx H, time states TSx L) originating from the CPU's timing generator.
   • CPU State: Indicates the major state of the CPU and the current instruction's op code.
   • Memory Timing Signals: Control all memory operations (e.g., SOURCE H, RETURN H, WRITE H, INHIBIT H, STROBE H).
   • Miscellaneous Signals: A collection of signals used by the operator's console, for memory stalling, and reporting power supply validity (POWER OK H).
3. Detailed Logic Description: Provides an in-depth explanation of the function and operation of each of the 96 OMNIBUS signal lines.
4. Timing: Specifies critical timing relationships, including the characteristics of time pulses and states, memory timing, I/O timing (basic and expanded), and data break timing. It addresses bus capacitance and signal settling times.
5. Electrical Characteristics and Interfacing: Defines logic voltage levels, bus load requirements, driving capabilities for signals (e.g., open-collector outputs, sink currents), and recommendations for using high-impedance receivers and load relief techniques to manage bus reflections and loading effects.
6. Power Supply Requirements: Outlines the voltage tolerances, regulation, and over-voltage protection necessary for the +5V, +15V, and -15V supplies, along with the function of the POWER OK H signal.
7. Signal Index and References: Includes a comprehensive index of all OMNIBUS signal names, their associated pins, and references to relevant sections, along with a glossary of external reference documents.

In essence, the document serves as the definitive guide for engineers to ensure compatibility and proper function when integrating new circuit modules or peripherals with the OMNIBUS in PDP-8 series mini-computers.